1. Field
The present application relates generally to the design and operation of clock generation circuits, and more particularly, to methods and apparatus for a gray-coded phase rotating frequency divider.
2. Background
Clock generation circuits, such as phase-locked loops (PLLs), have a wide range of applications in radio, telecommunications, computers, and other electronic systems. A phase-locked loop circuit compares the phase of an input reference signal with a phase signal derived from the PLL's output oscillator and attempts to adjust the frequency of the oscillator to keep the phases matched. Typically, phase-locked loops comprise a phase detector, low pass filter and voltage-controlled oscillator (VCO) in a closed-loop configuration. A divide-by-N frequency divider may be used in the feedback path to make the PLL's output signal frequency an integer multiple of the reference. A frequency divider that switches back and forth between two integer division ratios produces a non-integer multiple of the reference frequency to form what is typically referred to as a fractional-N PLL.
Conventional frequency dividers may utilize a binary phase rotator design that has inherent linearity problems and reduced frequency of operation. For example, a binary phase rotator may introduce systematic timing errors when dividing by other than multiples of four. As a result, nonlinearity in the feedback divider may cause noise folding into the in-band of the PLL.
Therefore, it would be desirable to have a frequency divider system that overcomes the problems associated with conventional frequency dividers.